Fabricating process of circuit substrate and circuit substrate structure
US8431454B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 26, 2011 |
| Grant date | Apr 30, 2013 |
| Priority date | — |
| Expiry date | Aug 24, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/856
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fabricating process of circuit substrate sequently includes: providing a substrate with a pad and a dielectric stack layer disposed at the substrate and overlaying the pad, in which the stack layer includes two dielectric layers and a third dielectric layer located between the two dielectric layers, and the etching rate of the third dielectric layer is greater than the etching rate of the two dielectric layers; forming an opening corresponding to the pad at the stack layer; performing a wet etching process on the stack layer to remove the portion of the third dielectric layer surrounding the opening to form a gap between the portions of the two dielectric layers surrounding the opening; performing a plating process on the stack layer and the pad to respectively form two plating layers at the stack layer and the pad, in which the gap isolates the two plating layers from each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.