Nonvolatile memory devices including deep and high density trapping layers
US8431984B2 · kind B2 · utility
4Cited by
5References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2011 |
| Grant date | Apr 30, 2013 |
| Priority date | — |
| Expiry date | Aug 31, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A charge trap nonvolatile memory device includes a gate electrode on a substrate; a charge trapping layer between the gate electrode and the substrate, the charge trapping layer having trap sites configured to trap charges; a charge tunneling layer between the trapping layer and the semiconductor substrate; and a charge blocking layer between the gate electrode and the trapping layer. The charge trapping layer comprises a deep trapping layer having a plurality of energy barriers and a high density trapping layer having a trap site density higher than a trap site density of the deep trapping layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.