Low capacitance transient voltage suppressor
US8431999B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2011 |
| Grant date | Apr 30, 2013 |
| Priority date | — |
| Expiry date | Dec 21, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D8/00
Abstract
A low capacitance transient voltage suppressor is disclosed. The suppressor comprises an N-type heavily doped substrate and an epitaxial layer formed on the substrate. At least one steering diode structure formed in the epitaxial layer comprises a diode lightly doped well and a first P-type lightly doped well, wherein a P-type heavily doped area is formed in the diode lightly doped well and a first N-type heavily doped area and a second P-type heavily doped area are formed in the first P-type lightly doped well. A second P-type lightly doped well having two N-type heavily doped areas is formed in the epitaxial layer. In addition, an N-type heavily doped well and at least one deep isolation trench are formed in the epitaxial layer, wherein the trench has a depth greater than or equal to depths of all the doped wells, so as to separate at least one doped well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.