Latch circuits with synchronous data loading and self-timed asynchronous data capture
US8432195B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2010 |
| Grant date | Apr 30, 2013 |
| Priority date | — |
| Expiry date | Jan 27, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356104
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A latch integrated circuit has synchronous data loading and self-timed asynchronous data capture characteristics. The integrated circuit may include a latch, a pulse generator and a comparator. The latch can be responsive to a data signal and a write enable signal. The pulse generator may be configured to generate the write enable signal as a pulse. This pulse may have a leading edge synchronized with a first edge of a clock signal and a self-timed trailing edge synchronized with an edge of a comparison signal. The comparator may be configured to generate the comparison signal in response to comparing logic levels of at least two nodes within the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.