Patent · US Active

Fractional digital PLL with analog phase error compensator

US8432199B2 · kind B2 · utility

13Cited by

4References

5Claims

0Family size

Assignee

KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY · KR

Inventors

Ja Yol Lee · Daejeon, KR
Seong Do Kim · Daejeon, KR
Hyun-Kyu Yu · Suwon-si, KR

Key dates

Filing date	Dec 2, 2011
Grant date	Apr 30, 2013
Priority date	—
Expiry date	Dec 2, 2031

Classification

Technology area (CPC H)Electricity
CPC primaryH03L2207/50
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Disclosed is a fractional digital phase locked loop with an analog phase error compensator. The digital phase locked loop with an analog phase error compensator can reduce excessive power consumption and power noise and transient current noise while increasing phase error detection resolution by performing fractional phase error detection and compensation through the analog phase error compensator.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.