Data rate buffering in display port links
US8432408B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 7, 2010 |
| Grant date | Apr 30, 2013 |
| Priority date | — |
| Expiry date | Sep 16, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N7/0105
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Rate matching for use in data links between a source device and a sink device is provided. A rate matching device includes a first-in-first-out (FIFO) buffer having a write pointer and a read pointer; a write control having a write clock to write an input data stream from the source device onto the FIFO buffer using the write pointer; a read control having a read clock to read data from the FIFO buffer using a read pointer, insert data to an output data stream and transmitting the data stream to the sink device; a processor to provide a bit number based on the write clock period and the read clock period, wherein the read control inserts blanking data into the output data stream while the read pointer is stopped in the FIFO buffer to allow the write pointer to move ahead by the bit number provided by the processor. Some embodiments are thus able to avoid buffer overflow or underflow scenarios.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.