Digital phase-locked loop with gated time-to-digital converter
US8433025B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2008 |
| Grant date | Apr 30, 2013 |
| Priority date | — |
| Expiry date | May 27, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/087
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital PLL (DPLL) includes a time-to-digital converter (TDC) and a control unit. The TDC is periodically enabled for a short duration to quantize phase information and disabled for the remaining time to reduce power consumption. The TDC receives a first clock signal and a first reference signal and provides a TDC output indicative of the phase difference between the first clock signal and the first reference signal. The control unit generates an enable signal based on a main reference signal and enables and disables the TDC with the enable signal. In one design, the control unit delays the main reference signal to obtain the first reference signal and a second reference signal, generates the enable signal based on the main reference signal and the second reference signal, and gates a main clock signal with the enable signal to obtain the first clock signal for the TDC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.