Interruptible write block and method for using same
US8433857B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 12, 2008 |
| Grant date | Apr 30, 2013 |
| Priority date | — |
| Expiry date | Mar 1, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A disclosed embodiment is an interruptible write block comprising a primary register having an input coupled to an input of the interruptible write block, a secondary register having an input selectably coupled to an output of the primary register and to an output of the secondary register through an interrupt circuit. The interrupt circuit is utilized to interrupt flow of new data from the primary register to the secondary register during an interrupt of a write operation, such that upon resumption of the write operation the secondary register contains valid data. A method of utilizing an interruptible write block during a write operation comprises loading data into a primary register, interrupting the write operation to perform one or more other operations, loading the data into a secondary register while loading new data into the primary register, and resuming the write operation using valid data from the secondary register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.