Apparatus and method for buffer management for a memory operating
US8433859B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 2008 |
| Grant date | Apr 30, 2013 |
| Priority date | — |
| Expiry date | Nov 29, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention provides a buffer management apparatus coupled between a memory and a plurality of circuit blocks accessing the memory. In one embodiment, the buffer management apparatus comprises an arbiter, a plurality of buffers, and a multiplexer. The arbiter selects a plurality of owners for the buffers from the circuit blocks, passes a plurality of access request signals generated by the owners to the corresponding buffers, and delivers a plurality of access response signals retrieved from the corresponding buffers to the owners in reply to the access request signals. The multiplexer alternately retrieves the access request signals from the buffers to generate a memory access signal delivered to a memory controller of the memory, receives a memory response signal generated by the memory controller in reply to the memory access signal, and distributes the memory response signal to the buffers as the access response signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.