Clock divider system and method with incremental adjustment steps while controlling tolerance in clock duty cycle
US8433944B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2010 |
| Grant date | Apr 30, 2013 |
| Priority date | — |
| Expiry date | Jun 27, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K21/38
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a particular embodiment, a single step increment calculation module is responsive to a first ramp control value and a second ramp control value. The single step increment calculation module generates a single step frequency adjustment as an output. The generated single step frequency adjustment is applied to a system clock signal having a first frequency to change the system clock signal to a second clock signal having a second frequency. The first frequency is different from the second frequency and the system clock signal has a first duty cycle that is within a tolerance range of a second duty cycle of the second clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.