System to determine fault tolerance in an integrated circuit and associated methods
US8433950B2 · kind B2 · utility
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28Claims
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Key dates
| Filing date | Mar 17, 2009 |
| Grant date | Apr 30, 2013 |
| Priority date | — |
| Expiry date | Nov 5, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system to determine fault tolerance in an integrated circuit may include a programmable logic device carried by the integrated circuit. The system may also include a configurable memory carried by the programmable logic device to control the function and/or connection of a portion of the programmable logic device. The system may further include user logic carried by said programmable logic device and in communication with a user and/or the configurable memory. The user logic may identify corrupted data in the configurable memory based upon changing user requirements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.