Coding across data blocks to reduce write amplification in NAND flash
US8433981B1 · kind B1 · utility
9Cited by
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22Claims
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Key dates
| Filing date | Dec 2, 2010 |
| Grant date | Apr 30, 2013 |
| Priority date | — |
| Expiry date | Oct 6, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1068
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Data is stored from a host. A flash memory is divided into a plurality of memory groups, the memory groups each comprising a plurality of flash memory blocks. A first portion of one of the plurality of memory groups is allocated for storing parity data of an error-correcting code for the memory group. A second portion of the memory group is allocated for storing data from the host. A flash memory block in the memory group is erased prior to writing the data from the host, wherein the flash memory block contains valid data. The erased valid data is recovered using the error-correcting code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.