Methods of manufacturing semiconductor devices
US8435877B2 · kind B2 · utility
3Cited by
1References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2011 |
| Grant date | May 7, 2013 |
| Priority date | — |
| Expiry date | Sep 8, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes gate structures including a tunnel insulating layer pattern, a floating gate, a dielectric layer pattern and a control gate sequentially disposed on a substrate. The control gate includes an impurity doped polysilicon layer pattern and a metal layer pattern. The gate structures are spaced apart from each other on the substrate. A capping layer pattern is disposed on a sidewall portion of the metal layer pattern and includes a metal oxide. An insulating layer covers the gate structures and the capping layer pattern. The insulating layer is formed on the substrate and includes an air-gap therein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.