Method for manufacturing a transistor

US8435900B2 · kind B2 · utility

Assignee

• Semiconductor Manufacturing International Corp. · CN

Inventors

• Qun Shao · Shanghai, CN
• Zhongshan Hong · Shanghai, CN

Key dates

• Filing date: Sep 23, 2011
• Grant date: May 7, 2013
• Expiry date: Jan 25, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0147
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The invention provides a method for manufacturing a transistor which includes: providing a substrate having a plurality of transistors formed thereon, wherein each transistor includes a gate; forming a stressed layer and a first oxide layer on the transistors and on the substrate successively; forming a sacrificial layer on the first oxide layer; patterning the sacrificial layer to remove a part of the sacrificial layer which covers on the gates of the transistors; forming a second oxide layer on the residual sacrificial layer and on a part of the first oxide layer which is exposed after the part of the sacrificial layer is removed; performing a first planarization process to remove a part of the second oxide layer located on the gates of the transistors; performing a second planarization process to remove the residual second oxide layer; and performing a third planarization process to remove the stressed layer.