Reconfigurable logic block with user RAM
US8436646B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2011 |
| Grant date | May 7, 2013 |
| Priority date | — |
| Expiry date | Sep 8, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17724
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device includes logic blocks such as a logic array blocks (LAB) that can be configured as a random access memory (RAM) or as a lookup table (LUT). A mode flag is provided to indicate the mode of operation of configuration logic such as a configuration RAM (CRAM) used during partial reconfiguration of a logic block. If the mode flag indicates a design state, the configuration logic associated with the logic block is included in data verification and correction processes. If the mode flag indicates a user defined state, the configuration logic associated with the logic block is excluded from data verification and correction processes. Thus, exclusion and inclusion of portions of a region of configuration logic from data verification and correction processes allow a region of configuration logic to store both a design state and a user defined state without causing deleterious effects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.