Dual-edge register and the monitoring thereof on the basis of a clock
US8436652B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 2, 2011 |
| Grant date | May 7, 2013 |
| Priority date | — |
| Expiry date | Jun 2, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/037
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Sequential electronic circuit (10) reacting on a rising edge and a falling edge of a clock signal (CK), comprising a first (1) and a second (2) D-type flip-flop, a main multiplexer (3) coupled at input to the flip-flops (1 and 2), the circuit (10) comprising a first input receiving the clock signal (CK) and a second input receiving a control signal (TE) so as to control the circuit (10) according to a normal operating mode and a test operating mode making it possible to check the proper operation of the sequential electronic circuit (10). The clock signal (CK) used in the normal operating mode is used to gate the circuit (10) during the test operating mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.