Load-line adaptation
US8436694B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 8, 2009 |
| Grant date | May 7, 2013 |
| Priority date | — |
| Expiry date | Dec 3, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/471
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
According to the general concept disclosed herein, a circuit for adaptive matching of a load impedance to a predetermined load-line impedance of a load-line connected to a power amplifier output includes a fixed matching network between the power transistor and an adaptive matching network, whereby the fixed matching network acts as an impedance inverter which results in a relatively low insertion loss at high power. Results indicate that the impedance-inverting network can be used over more than a factor of 10 in impedance variation. Further, the usage of the fixed matching network, close to the power transistor, allows for the implementation of transmission zeros and/or for a well defined load impedance at a predetermined harmonic frequency, independent of the (variable) load impedance at the fundamental frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.