Zeroization verification of integrated circuit
US8437200B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2011 |
| Grant date | May 7, 2013 |
| Priority date | — |
| Expiry date | Nov 11, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17768
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and circuits for zeroization verification of the memory in an integrated circuit (IC) are provided. One method includes sequentially reading frames from a block of the memory, and sequentially performing a logical operation between each of the frames and the content of a signature register. The result of the logical operation is stored back in the signature register. In another operation, a hardware logical comparison is made between a device hardwired signature block and the content of the signature register, after the logical operations for all the frames have been performed. The device hardwired signature block is a hardware implemented constant that is unavailable for loading in registers of the IC. The block of the memory is verified to hold a fixed value when the result of the hardware logical comparison indicates that the device hardwired signature block is equal to the content of the signature register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.