Firmware processing for downlink F-DPCH
US8437315B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2007 |
| Grant date | May 7, 2013 |
| Priority date | — |
| Expiry date | Sep 3, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04W52/545
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A downlink channel receiver operable to implement fractional dedicated physical channel (F-DPCH) processing within a Rake receiver structure is provided. The downlink channel receiver includes a receiver, a baseband processing block, a WCDMA processing block, wherein F-DPCH processing is divided between a plurality of hardware processing blocks and a plurality of firmware (FW) processing blocks. The receiver is operable to convert a radio frequency (RF) signal to a baseband signal. The baseband processing block operable to processes and provides the baseband signal to the WCDMA processing block. F-DPCH processing is divided between the plurality of hardware processing blocks and plurality of firmware (FW) processing blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.