Data latch circuit and method of a low power decision feedback equalization (DFE) system
US8437388B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2010 |
| Grant date | May 7, 2013 |
| Priority date | — |
| Expiry date | May 4, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0274
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Data latch circuit and method of low power decision feedback equalization (DFE) system is disclosed. In one embodiment, the data latch circuit of the of a decision feedback equalization (DFE) system includes a first parallel n-channel metal-oxide-semiconductor field-effect transistor (NMOS) pair to input a differential input voltage. The data latch circuit also includes a second parallel NMOS pair coupled to the first parallel NMOS pair to input a decision feedback equalization (DFE) voltage. The data latch circuit further includes a cross-coupled PMOS pair to generate a positive feedback to the first parallel NMOS pair and/or the second parallel NMOS pair. In addition, the data latch circuit includes a cross-coupled NMOS pair to escalate the positive feedback. Furthermore the data latch circuit includes a latching circuit to generate a signal data based on the sinking of a current at an input of the latching circuit and/or the positive feedback.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.