Adaptive precision arithmetic unit for error tolerant applications
US8438207B2 · kind B2 · utility
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14Claims
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Key dates
| Filing date | Sep 28, 2007 |
| Grant date | May 7, 2013 |
| Priority date | — |
| Expiry date | Jan 23, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Two process-tolerant arithmetic circuit architectures are implemented to develop functional blocks for error-tolerant applications such as FIR filters and FFT blocks. The resulting blocks may achieve computational performance of up to 42 times higher than conventional architectures. Embodiments adaptively change the precision of the computation to achieve a high precision computation given the underlying speed of the circuit. The resulting improvement can be allocated to increasing yield or dynamically trading off between reduced power consumption, faster computation, or higher-fidelity computation.
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