Various methods and apparatus for address tiling and channel interleaving throughout the integrated system
US8438320B2 · kind B2 · utility
8Cited by
28References
20Claims
0Family size
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Key dates
| Filing date | Oct 5, 2009 |
| Grant date | May 7, 2013 |
| Priority date | — |
| Expiry date | Mar 25, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4295
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various methods and apparatus are described for a target with multiple channels. Address decoding logic is configured to implement a distribution of requests from individual burst requests to two or more memory channels making up an aggregate target. The address decoding logic implements a channel-selection hash function to allow requests from each individual burst request to be distributed amongst the two or more channels in a non-linear sequential pattern in channel round order that make up the aggregate target.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.