Optimization of paging cache protection in virtual environment
US8438363B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2012 |
| Grant date | May 7, 2013 |
| Priority date | — |
| Expiry date | Apr 30, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2009/45583
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system, method and computer program product for virtualizing a processor include a virtualization system running on a computer system and controlling memory paging through hardware support for maintaining real paging structures. A Virtual Machine (VM) is running guest code and has at least one set of guest paging structures that correspond to guest physical pages in guest virtualized linear address space. At least some of the guest paging structures are mapped to the real paging structures. A cache of connection structures represents cached paths to the real paging structures. The mapped paging tables are protected using RW-bit. A paging cache is validated according to TLB resets. Non-active paging tree tables can be also protected at the time when they are activated. Tracking of access (A) bits and of dirty (D) bits is implemented along with synchronization of A and D bits in guest physical pages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.