Via-node-based electromigration rule-check methodology
US8438519B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 4, 2008 |
| Grant date | May 7, 2013 |
| Priority date | — |
| Expiry date | May 10, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of method of manufacturing an integrated circuit. The method comprises performing an electromigration reliability rule-check for at least one of via node of an integrated circuit, including: calculating a net effective current density of the via node. Calculating the net effective current density including determining a sum of effective current densities for individual leads that are coupled to the via node. Leads configured to transfer electrons away from said via node are assigned a positive polarity of the effective current density. Leads configured to transfer electrons towards the via node are assigned a negative polarity of the effective current density.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.