Logic element architecture for generic logic chains in programmable devices
US8438522B1 · kind B1 · utility
3Cited by
167References
14Claims
0Family size
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Key dates
| Filing date | Sep 24, 2008 |
| Grant date | May 7, 2013 |
| Priority date | — |
| Expiry date | Mar 17, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reconfigurable device includes an arrangement of a plurality of cells and routing resources for transmitting signals between the cells. The plurality of cells comprises carry-select reuse cells, each of the carry-select reuse cells configured to provide for performing non-arithmetic operations using a reuse arithmetic carry chain interconnecting adjacent cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.