Method of fabricating memory
US8440526B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2011 |
| Grant date | May 14, 2013 |
| Priority date | — |
| Expiry date | Jan 10, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76897
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a memory is provided. A substrate including a memory region and a periphery region is provided. A plurality of first gates is formed in the memory region and a plurality of first openings is formed between the first gates. A nitride layer is formed on the substrate in the memory region, and the nitride layer covers the first gates and the first openings. An oxide layer is formed on the substrate in the periphery region. A nitridization process is performed to nitridize the oxide layer into a nitridized oxide layer. A conductive layer is formed on the substrate, and the conductive layer includes a cover layer disposed on the substrate in the memory region and a plurality of second gates disposed on the substrate in the periphery region. The cover layer covers the nitride layer and fills the first openings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.