Thin-film transistor, display device, and manufacturing method for thin-film transistors
US8441016B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2010 |
| Grant date | May 14, 2013 |
| Priority date | — |
| Expiry date | Jul 12, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6717
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Disclosed is a high-quality, efficiently manufacturable thin film transistor in which leakage current is minimized. The thin film transistor is provided with a semiconductor layer (34) that contains a channel region (34C) having a microcrystalline semiconductor; source and drain contact layers (35S and 35D) that contains impurities; a first source metal layer (36S) and a first drain metal layer (36D), and a second source metal layer (37S) and a second drain metal layer (37D). The end portion of the second metal source layer (37S) is located at a position receded from the end portion of the first metal source layer (36S) and the end portion of the second drain metal layer (37D) is located at a position receded from the end portion of the first drain metal layer (36D). The semiconductor layer (34) contains low concentration impurity diffusion regions formed near the end portions of the aforementioned source contact layer (35S) and drain contact layer (35D).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.