Power device with low parasitic transistor and method of making the same
US8441067B2 · kind B2 · utility
1Cited by
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14Claims
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Inventor
Key dates
| Filing date | Mar 24, 2011 |
| Grant date | May 14, 2013 |
| Priority date | — |
| Expiry date | Apr 18, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/517
Abstract
The power device with low parasitic transistor comprises a recessed transistor and a heavily doped region at a side of a source region of the recessed transistor. The conductive type of the heavily doped region is different from that of the source region. In addition, a contact plug contacts the heavily doped region and connects the heavily doped region electrically. A source wire covers and contacts the source region and the contact plug to make the source region and the heavily doped region have the same electrical potential.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.