Power factor correction (PFC) circuit and method therefor
US8441237B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2010 |
| Grant date | May 14, 2013 |
| Priority date | — |
| Expiry date | Sep 11, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Consistent with an example embodiment, a circuit comprises a power factor correction stage having a DC input, a ground input, a DC output and a ground output. The circuit further includes a capacitor; a diode; and a discharge circuit. A first terminal of the diode is connected to an input of the power factor correction stage, a second terminal of the diode is connected to the first plate of the capacitor; and the second plate of the capacitor is connected to the other input of the PFC stage. The discharge circuit is connected to the capacitor and is configured to discharge the capacitor such that it contributes to the output of the PFC stage when the level of a signal at the input of the PFC stage falls below a threshold value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.