Patent · US Active

PLL using interpolative divider as digitally controlled oscillator

US8441291B2 · kind B2 · utility

13Cited by

6References

19Claims

0Family size

Assignee

Silicon Laboratories Inc. · US

Inventors

Susumu Hara · Austin, US
Adam B. Eldredge · Austin, US
Zhuo Fu · Austin, US
James Wilson · Maple Valley, US

Key dates

Filing date	Sep 23, 2011
Grant date	May 14, 2013
Priority date	—
Expiry date	Sep 23, 2031

Classification

Technology area (CPC H)Electricity
CPC primaryH03L7/1974
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

One or more PLLs are formed on an integrated circuit. Each PLL includes an interpolative divider configured as a digitally controlled oscillator, which receives a reference clock signal and supplies an output signal divided according to a divide ratio. A feedback divider is coupled to the output signal of the interpolative divider and supplies a divided output signal as a feedback signal. A phase detector receives the feedback signal and a clock signal to which the PLL locks. The phase detector supplies a phase error corresponding to a difference between the clock signal and the feedback signal and the divide ratio is adjusted according to the phase error.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.