Delaying data signals
US8441292B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2010 |
| Grant date | May 14, 2013 |
| Priority date | — |
| Expiry date | Nov 8, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M9/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment, multiple (serializer/deserializer) SERDES channels are aligned by selectively slipping one or more of the incoming serial data streams one bit at a time prior to deserialization. Within each SERDES channel, a slip circuit slips the corresponding serial data stream by one bit (i.e., one unit interval (UI)) by extending the high portion of the duty cycle of a corresponding clock signal. The high portion of the clock signal is extended using a 3-to-1 mux that selects a fixed high signal, such as the high power supply rail, as an intermediate mux output signal whenever transitioning between two different applied clock signals that are offset from one another by one UI. In this way, the slip circuit avoids glitches that might otherwise result from switching directly between the two clock signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.