Simultaneous data packet processing
US8441947B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2009 |
| Grant date | May 14, 2013 |
| Priority date | — |
| Expiry date | Dec 19, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L43/50
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A packet controller for simultaneous processing of data packets transmitted via a plurality of communication channels includes a plurality of inputs to receive a respective plurality of signals, such that each of the plurality of signals is indicative of a presence of a data packet on a respective one of the plurality of communication channels, a clock source to supply a periodic clock signal, a plurality of independent processing modules coupled to the respective plurality of inputs to simultaneously process the plurality of signals, such that each of the plurality of independent processing modules implements a respective state machine driven by the periodic clock signal to process the respective signal independently of every other one of the plurality of processing modules, and an output to transmit an output signal indicative of a presence of at least one data packet on one or more of the plurality of communication channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.