Bit plane encoding/decoding system and method for reducing spatial light modulator image memory size
US8442332B2 · kind B2 · utility
0Cited by
5References
12Claims
0Family size
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Key dates
| Filing date | Dec 14, 2007 |
| Grant date | May 14, 2013 |
| Priority date | — |
| Expiry date | Dec 11, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/18
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A bit plane generating system, a method of generating a bit plane and an integrated circuit incorporating the system or the method. In one embodiment, the bit plane generating system includes: (1) a memory configured to store pixel data pertaining to an image to be displayed and (2) bit plane decoding circuitry coupled to the memory and configured to transform the pixel data into at least a portion of a bit plane in accordance with a signal received from a sequence controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.