Multiplication circuit and de/encryption circuit utilizing the same
US8443032B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2008 |
| Grant date | May 14, 2013 |
| Priority date | — |
| Expiry date | Mar 14, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/57
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiplication circuit generates a product of a matrix and a first scalar when in matrix mode and a product of a second scalar and a third scalar when in scalar mode. The multiplication circuit comprises a sub-product generator, an accumulator and an adder. The adder is configured to sum outputs of the accumulator to generate the product of the first scalar second scalar and the third scalar when in scalar mode. The sub-product generator generates sub-products of the matrix and the first scalar when in matrix mode and sub-products of the second scalar and the third scalar when in scalar mode. The accumulator is configured to generate the product of the matrix and the first scalar by providing save of the multiplication operation of the outputs from the sub-product generator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.