Data storage device employing a run-length mapping table and a single address mapping table
US8443167B1 · kind B1 · utility
253Cited by
30References
24Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 16, 2009 |
| Grant date | May 14, 2013 |
| Priority date | — |
| Expiry date | Sep 16, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data storage device is disclosed comprising a non-volatile memory comprising a plurality of memory segments. When a write command comprising a logical block address (LBA) is received, a number of consecutive memory segments to access in response to the write command is determined. When the number of consecutive memory segments to access is greater than a threshold, a new run-length mapping entry in a run-length mapping table (RLMT) is created. When the number of memory segments to access is not greater than a threshold, at least one new single address mapping entry in a single address mapping table (SAMT) is created.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.