Secure function evaluation techniques for circuits containing XOR gates with applications to universal circuits
US8443205B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2008 |
| Grant date | May 14, 2013 |
| Priority date | — |
| Expiry date | Mar 7, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/46
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An embodiment of the present invention provides a method that minimizes the number of entries required in a garbled circuit associated with secure function evaluation of a given circuit. Exclusive OR (XOR) gates are evaluated in accordance with an embodiment of the present invention without the need of associated entries in the garbled table to yield minimal computational and communication effort. This improves the performance of SFE evaluation. Another embodiment of the present invention provides a method that replaces regular gates with more efficient constructions containing XOR gates in an implementation of a Universal Circuit, and circuits for integer addition and multiplication, thereby maximizing the performance improvement provided by the above.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.