Apparatus, system, and method for using multi-level cell solid-state storage as single level cell solid-state storage
US8443259B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2012 |
| Grant date | May 14, 2013 |
| Priority date | — |
| Expiry date | Jun 22, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus, system, and method are disclosed for storing information in a storage device that includes multi-level memory cells. The method involves storing data that is written to the storage device in the LSBs of the multi-level memory cells, and storing audit data in the MSBs of the multi-level memory cells. The audit data can be read separately from the data and used to determine whether or not there has been any unintended drift between states in the multi-level cells. The audit data may be used to correct data when the errors in the data are too numerous to be corrected using error correction code (ECC). The audit data may also be used to monitor the general health of the storage device. The monitoring process may run as a background process on the storage device. The storage device may transition the multi-level memory cells to operate as single-level memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.