Multiple input hardware reuse using LDPC codes
US8443270B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2008 |
| Grant date | May 14, 2013 |
| Priority date | — |
| Expiry date | Aug 11, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/005
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A network controller receives data substantially simultaneously from multiple client nodes. The network controller assigns to each client node one or more sub-carriers of an orthogonal frequency-division multiplexing access frequency spectrum. The client nodes transmit substantially simultaneously M LDPC codewords that are encoded in a parity check matrix so that the number of rows m′ depend on the code rate and are mapped on its assigned sub-carriers. The network controller computes a bit log-likelihood ratio for each received bit of the codewords and arranges the bit LLR by codeword to align with an equivalent parity check matrix. The network controller decodes the codewords with the equivalent parity check matrix.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.