Method and system for implementing a structure to implement I/O rings and die area estimations
US8443323B1 · kind B1 · utility
5Cited by
23References
48Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2010 |
| Grant date | May 14, 2013 |
| Priority date | — |
| Expiry date | Apr 2, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are improved methods, systems, and computer program products for implementing an I/O ring structure to generate an I/O ring arrangement for an electronic design, and for performing chip planning and estimation based upon the I/O ring arrangement. Nodes in the I/O ring structure are used to track objects in the I/O ring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.