Methods and apparatus for a configurable protection architecture for on-chip systems
US8443422B2 · kind B2 · utility
19Cited by
39References
20Claims
0Family size
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Key dates
| Filing date | Sep 1, 2010 |
| Grant date | May 14, 2013 |
| Priority date | — |
| Expiry date | Oct 22, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various methods and apparatuses of protection mechanism are described. A target intellectual property block may field and service requests from an initiator intellectual property block in a system-on-chip network. The target intellectual property block has an associated protection mechanism with logic configured to restrict access for the requests to the target intellectual property block. The request's access is restricted based on access permissions associated with a region within the target intellectual property block and attributes of the request trying to access that region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.