Side wall pore sealing for low-k dielectrics
US8445382B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 20, 2006 |
| Grant date | May 21, 2013 |
| Priority date | — |
| Expiry date | Jun 20, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1063
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A dual damascene process for forming conductive interconnects on an integrated circuit die. The process includes providing a layer (16) of porous, ultra low-k (ULK) dielectric material in which a via opening (30) is subsequently formed. A thermally degradable polymeric (“porogen”) material (42) is applied to the side wall sidewalls of the opening (30) such that the porogen material penetrates deeply into the porous ULK dielectric material (thereby sealing the pores and increasing the density thereof). Once a conductive material (36) has been provided with the opening (30) and polished back by means of chemical mechanical polishing (CMP), the complete structure is subjected to a curing step to cause the porogen material (44) with the ULK dielectric layer (16) to decompose and evaporate, thereby restoring the porosity (and low-k value) of the dielectric layer (16).Attached are a marked-up copy of the originally filed specification and a clean substitute specification in accordance with 37 C.F.R. §§1.121(b)(3) and 1.125(c). Applicant respectfully submits that the substitute specification contains no new matter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.