High-performance gate oxides such as for graphene field-effect transistors or carbon nanotubes
US8445893B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2010 |
| Grant date | May 21, 2013 |
| Priority date | — |
| Expiry date | Jan 15, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/882
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An apparatus or method can include forming a graphene layer including a working surface, forming a polyvinyl alcohol (PVA) layer upon the working surface of the graphene layer, and forming a dielectric layer upon the PVA layer. In an example, the PVA layer can be activated and the dielectric layer can be deposited on an activated portion of the PVA layer. In an example, an electronic device can include such apparatus, such as included as a portion of graphene field-effect transistor (GFET), or one or more other devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.