Source and drain feature profile for improving device performance
US8445940B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2012 |
| Grant date | May 21, 2013 |
| Priority date | — |
| Expiry date | Jul 9, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02639
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device is disclosed. The disclosed device provides improved control over a surface proximity and tip depth of integrated circuit devices. An exemplary integrated circuit device disclosed herein has a surface proximity of about 1 nm to about 3 nm and a tip depth of about 5 nm to about 10 nm. The integrated circuit device having such surface proximity and tip depth includes an epi source feature and an epi drain feature defined by a first facet and a second facet of a substrate in a first direction, such as a {111} crystallographic plane of the substrate, and a third facet of the substrate in a second direction, such as a {100} crystallographic plane of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.