Solder bump interconnect
US8446019B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2012 |
| Grant date | May 21, 2013 |
| Priority date | — |
| Expiry date | Jul 9, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a device pad on a substrate. A first polymer layer overlies the substrate, and the first polymer layer has an opening to expose the device pad. In one embodiment, a redistribution layer (RDL) comprises a landing pad, and the RDL is positioned on the first polymer layer and conductively coupled to the device pad. A second polymer layer is on the RDL, and an under bump metal pad (UBM) is on the landing pad and extends onto a top surface of the second polymer layer. In one embodiment, a shortest distance from a center of the landing pad to an outer edge of the landing pad, and a shortest distance from a center of the UBM to an outer edge of the UBM are in a ratio that ranges from 0.5:1 up to 0.95:1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.