FPGA RAM blocks optimized for use as register files
US8446170B2 · kind B2 · utility
0Cited by
7References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 3, 2012 |
| Grant date | May 21, 2013 |
| Priority date | — |
| Expiry date | May 3, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1776
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A random access memory circuit adapted for use in a field programmable gate array integrated circuit device is disclosed. The FPGA has a programmable array with logic modules and routing interconnects programmably coupleable to the logic modules and the RAM circuit. The RAM circuit has three ports: a first readable port, a second readable port, and a writeable port. The read ports may be programmably synchronous or asynchronous and have a programmably bypassable output pipeline register. The RAM circuit is especially well adapted for implementing register files. A novel interconnect method is also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.