Phase locked loop with digital compensation for analog integration
US8446191B2 · kind B2 · utility
11Cited by
31References
38Claims
0Family size
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Key dates
| Filing date | Dec 7, 2009 |
| Grant date | May 21, 2013 |
| Priority date | — |
| Expiry date | May 28, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/093
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop (PLL) device includes a digital differentiator configured to differentiate a digital loop signal to at least partially compensate for the integration of an analog current signal by an analog integrator. A digital to analog converter (DAC) includes a current source output stage that generates the analog current signal based on an digital input signal. The analog integrator integrates the analog current signal to generate a voltage control signal for controlling a voltage controlled oscillator (VCO).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.