Digital background calibration system and method for successive approximation (SAR) analogue to digital converter
US8446304B2 · kind B2 · utility
16Cited by
9References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 30, 2011 |
| Grant date | May 21, 2013 |
| Priority date | — |
| Expiry date | Sep 6, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/804
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention provides a digital background calibration system and method for a successive approximation analog-to-digital converter comprising a digital to analog converter (DAC) having a plurality of weighted capacitors to be calibrated; means for splitting each of said weighted capacitors into a plurality of sub-capacitors and at least one redundant capacitor; means for multiplying the voltage level of at least one of the sub-capacitors with a PN sequence; and means for calibrating the weighted capacitor from the multiplied sub-capacitor and the redundant capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.