Comparator noise reduction by means of a programmable bandwidth
US8446307B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2011 |
| Grant date | May 21, 2013 |
| Priority date | — |
| Expiry date | Nov 23, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/2481
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A comparator including a preamplifier amplifying a first signal and a second signal to produce a first amplified signal on a first output terminal and a second amplified signal on a second output terminal. The comparator also includes a capacitor, a clamp and a latch coupled in parallel to the first output terminal and the second output terminal of the preamplifier. A control circuit is coupled to the variable capacitor and the clamp and is configured to close the clamp during a first time period to cause the first amplified signal and the second amplified signal to bypass the capacitor and the latch, and open the clamp during a second time period following the first time period to cause the first amplified signal and the second amplified signal to be coupled to the capacitor and the latch. The capacitor filters the amplified signals, and the latch produces a digital output signal of the comparator based on the filtered signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.