Content addressable memories with wireline compensation
US8446748B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2011 |
| Grant date | May 21, 2013 |
| Priority date | — |
| Expiry date | Nov 14, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
What is disclosed is a novel memory array and process for creating a memory array to reduce wireline variability. The method includes accessing a routing design of a memory array with a plurality of memory cells. Each memory cell in the array includes one or more access devices, and a group of wires electrically connected between one or more of the memory cells and peripheral circuitry (PC). The group of the group of wires is divided into at least one subgroup (N). Next, a capacitance (C1, C2 . . . CN) of each wire in the subgroup (N) is calculated. Continuing further, a maximum capacitance (CMAX) of wires in the subgroup (N) is determined. An add-on capacitance to be added to a number (NA) of the wires in the subgroup (N) is calculated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.