Method and system for reducing duty cycle distortion amplification in forwarded clocks
US8446985B2 · kind B2 · utility
0Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2008 |
| Grant date | May 21, 2013 |
| Priority date | — |
| Expiry date | Feb 23, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/061
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for reducing the amplification of the duty cycle distortion of high frequency clock signals when is provided. A data signal is sent to a receiver via a first channel. A clock signal is sent to the receiver via a second channel. The clock signal is filtered to substantially remove therefrom low frequency components before the clock signal is used by the receiver to recover data from the data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.